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For our thin film transistors, we use materials developed at PICM; such as: SiNx and SiOx for the gate dielectric (link to Dielectrics), microcrystalline silicon (link to microcrystalline silicon) or polymorphous silicon (link to polymorphous silicon) as the intrinsic semiconductor, and finally amorphous silicon as the N and P doped semiconductor.
The material studied should be deposited in the same reactor used in the actual display industry. The deposition rate and the uniformity of thin film are also important. Thin film transistors should have a very good electrical stability during display operation. Also high electron field mobility is important for OLED pixel. Mobility up to 2 or 3 cm²/V.s. should be enough. OFF current also is an important parameter for AMLCD and for AMOLED displays, this current should be less than 10pA.
In our group we have two aims: the first one is (i) to optimize the quality of the silicon layer and the quality of the interfaces between these different layers to have the best thin film transistors for displays application and (ii) to understand the mechanisms of different parameters and phenomena observed during the fabrication and electrical characterization of the Thin film transistor. The second aim is to realize CMOS electronic circuit like inverter, or amplifier based on thin film transistor.
(Electrical characterization of thin film transistor on rigid substrate)
We fabricate bottom gate thin film transistors, based on back channel etching technology (BCE). We use only four photolithography mask levels. The fabrication of these thin film transistors takes place in the shared clean room at Thales TRT. We used rigid substrates such as glass and flexible substrates such as PEN plastic.
For information on internships, doctoral studies, post-doctoral positions, or collaborations, please contact Dr. Maher Oudwan
The high surface-to-volume ratio and crystallinity of Si nanowires (SiNWs) makes them ideal for bio/chemical and mechanical sensor applications. Operating in a field effect transistor device, the channel current through the tiny SiNW is very sensitive to any change in surface charges produced by gas or bio molecules attachment or grafting. In order to scale up these SiNW-based sensor applications in a planar architecture (which is and probably will continue to be the mainstream in a foreseeable future), SiNWs need to be selectively addressed and precisely positioned for reliable device application.
In-plane SiNWs, produced via an in-plane solid-liquid-solid (IPSLS) growth mode, are well suited for this challenging task. The diameter of the in-plane SiNWs is readily controllable and can be scaled down to <15 nm. We have demonstrated successfully a precise growth-in-place of the in-plane SiNWs channels, realized in a CMOS compatible all-in-situ process. This provides a critical basis to move forward large-scale integration of various SiNWs-based functionalities.
1. Guiding growth kinetics, morphology and size control of the in-plane SiNWs devolopping in guiding mode.
2. Large-scale SiNW-based field effect transistor device integration, optimization and electrical characterization.
3. Surface functionalization and molecular grafting
For information on internships, doctoral studies, post-doctoral positions, or collaborations, please contact Dr Linwei YU